Embodiments of the present invention relate to circuits in general, and, in particular, to the routing of signals within circuits.
One of the critical factors for success in the design and development of integrated circuits is the ability to adapt to new functional requirements in next generation electronic products quickly. Additionally, it is useful if circuits can be reconfigured quickly to meet future design requirements. Previously, reconfigurable architectures included masked ROM, gate-arrays and analog arrays where logic, memory content, or interconnects could be changed by modifying certain process layers, typically the metal interconnect layers.
The introduction of non-volatile programming technology such as Electrically Programmable Read-Only Memory, EPROM, Electrically Erasable Programmable Read-Only Memory, EEPROM, and One-Time-Programmable (OTP) memory, allowed this reconfiguration to be done through electrical programming rather than through wafer fabrication and corresponding reticle changes. Such electrical programmability requires the use of passive switches, active switches, or both to reconfigure signal paths. Typically, the power and ground to the switches are not programmable. In some instances, this may be due to a substantially lower impedance requirement for power supply routing compared to the impedance of a programmable switch element. Therefore, various noise parameters may be introduced on these power supplies with their low impedance connections. The noise characteristics introduced may depend on which signals route through the switches connected to the power supply. In the case where multiple switches exist on a single power supply, noise may be coupled from one signal to another through the switches. Therefore, it may become important to find ways to minimize coupled noise. This may be especially true for clock circuits which may benefit from clean signal paths for clean signal propagation free from noise contamination by other signals.